ver.5 NJW1340 -1- video switch for dvd recorder general description package outline the NJW1340 is a video switch for dvd recorders corresponding to the composite signal and y/c signal. it contains synchronous separation circuit and synchronous signal detection circuit, which are operating constantly. therefore, it can detect a signal at the state of power save mode. features operating voltage 4.5 to 5.5v i 2 c bus interface 5-input 1-output video switch 3-input 1-output 2-circuit video switch 6th order low pass filter internal synchronous separation circuit internal synchronous signal detection circuit power save circuit bi-cmos technology package outline ssop32 block diagram NJW1340v gnd vcc 2 10 11 12 13 14 15 9 8 y in 1 y in 2 y in 3 gnd gnd gnd 1 2 3 6 5 4 c in 1 v cc 1 c in 2 c in 3 power save 7 lpf sync sepa out 2 27 26 23 22 sync detect 31 21 20 cvbs in 1 cvbs in 2 cvbs in 3 cvbs in 4 gnd det sw m.m tc m.m integ lpf out 1 29 16 18 17 19 det out 32 gnd cvbs in 5 28 i 2 c bus address sda scl 30 gnd bias bias bias clamp clamp clamp clamp clamp clamp clamp clamp 25 24 clamp clamp
NJW1340 - 2 - absolute maximum ratings (ta=25 c) (note1) at on a board of eia/jedec specification. (76.2 114.3 1.6mm two layers, fr-4) recommended opearating condition (ta=25 c) parameter symbol test condition min. typ. max. unit operating voltage vopr 4.5 5.0 5.5 v electrical characteristics (v + =5.0v, r l =10k ? , ta=25 c) parameter symbol test condition min. typ. max. unit operating current icc no signal - 13.0 17.0 ma operating current at power save isave power save - 5.0 6.5 ma maximum output voltage 1 vom1 clamp channel vin=100khz, 1.0vp-p sin signal, thd=1% 1.6 2.6 - vp-p maximum output voltage 2 vom2 bias channel vin=100khz, 1.0vp-p sin signal, thd=1% 1.6 2.9 - vp-p voltage gain gv vin=1mhz, 1.0vp-p sin signal -0.5 0.0 0.5 db frequency characteristic 1 gf1 vin=6mhz / 100khz, 1.0vp-p sin signal -0.5 0.0 0.5 db frequency characteristic 2 gf2 vin=27mhz / 100khz, 1.0vp-p sin signal - -40 -24 db cross talk 1 cti vin=4.43mhz,1.0vp-p sin signal - -70 - db cross talk 2 ctb vin=4.43mhz,1.0vp-p sin signal - -70 - db differential gain dg vin=1.0vp-p 10step video signal - 0.5 - % differential phase dp vin=1.0vp-p 10step video signal - 0.5 - deg s/n snv vin=1.0vp-p,100% white video signal - 65 - db sync detection level v sync vin=10step video signal - 80 - mvp-p capture voltage h v caph (note2) 2.07 2.22 2.37 v capture voltage l v capl (note2) 1.57 1.72 1.87 v lock voltage h v lockh (note2) 2.53 2.68 2.83 v lock voltage l v lockl (note2) 1.25 1.40 1.55 v det out output voltage h deth 4.9 5.0 - v det out output voltage l detl - 0.1 0.3 v switch change voltage h vthh 2.0 - v + v switch change voltage l vthl 0 - 0.6 v adr voltage h v adrh 3.5 - 5.0 v adr voltage l v adrl 0 - 1.0 v power save sw inflow current h i swph v=5v 150 220 300 ua power save sw inflow current l i swpl v=0.3v 4.0 7.0 11.0 ua det sw inflow current h i deth v=5v 80 110 150 ua det sw inflow current l i detl v=0.3v 0.2 2.0 6.0 ua parameter symbol ratings unit supply voltage v + 7.0 v power dissipation p d 800(note1) mw operating temperature range topr -40 to +85 c storage temperature range tstg -40 to +125 c
NJW1340 -3- sda scl t f t hd:st a t low t r t hd:dat t high t f t su:dat s t su:sta t hd:st a t sp t su:sto sr t r t buf p s mode switch functon power save mode h video switch block power save off (active) l video switch block power save on (mute) open video switch block power save on (mute) det sw mode h y in 1select l cvbs in 1 select open cvbs in 1 select i 2 c bus block characteristics (sda,scl) i 2 c bus load conditions standard mode: pull up resistance 4k ? (connected to +5v), load capacitance 200pf (connected to gnd) parameter symbol min typ max unit low level input voltage v il 0.0 - 1.5 v high level input voltage v ih 2.7 - 5.5 v low level output voltage (3ma at sda pin) v ol 0 - 0.4 v output fall time from v ihmin to v ilmax with a bus capacitancefrom 10pf to 400pf t of - - 250 ns input current each i/o pin with an input voltage between 0.1 and 0.9v ddmax i i -10 - 10 a capacitance for each i/o pin c i - - 10 pf scl clock frequency f scl - - 100 khz data transfer start minimum waiting time t hd:sta 4.0 - - s low level clock pulse width t low 4.7 - - s high level clock pulse width t high 4.0 - - s minimum start preparation waiting time t su:sta 4.7 - - s minimum data hold time t hd:dat 0 - - s minimum data preparation time t su:dat 250 - - ns rise time t r - - 1000 ns fall time t f - - 300 ns minimum stop preparation waiting time t su:sto 4.0 - - s data change minimum waiting time t buf 4.7 - - s capacitive load for each bus line c b - - 400 pf noise margin at the low level v nl 0.5 - - v noise margin at the high level v nh 1 - - v c b ; total capacitance of one bus line in pf (note2) v lockh v caph 5 v v cap l v lock l 0 v capture range lock range
NJW1340 - 4 - ? ? ? ? i 2 c bus format msb lsb msb lsb msb lsb s slave address a data a data a p 1bit 8bit 1bit 8bit 1bit 8bit 1bit 1bit s: starting term a: acknowledge bit p: ending term ? ? ? ? slave address r/w: set the write mode or read mode. adr : set the slave address by ?adr? terminal. slave address hex msb lsb - 1 0 0 0 0 0 adr r/w - r/w = 0 : write mode, adr = 0/1 - 1 0 0 1 0 1 0 0 94(h) 1 0 0 1 0 1 1 0 96(h) r/w = 1 : read mode, adr = 0/1 - 1 0 0 1 0 1 0 1 95(h) 1 0 0 1 0 1 1 1 97(h) ? ? ? ? control register table bit no. d7 d6 d5 d4 d3 d2 d1 d0 data sel sw1 sel sw2 sel sw3 ? ? ? ? ? ? : don?t care ? ? ? ? control register default value control register default value is all ?0?. bit no. d7 d6 d5 d4 d3 d2 d1 d0 data 0 0 0 0 0 0 0 0 ? instruction code sel sw1 sel sw2 sel sw3 out1 out2 0 0 0 cvbs in1 c in 1 0 0 1 cvbs in2 c in 1 0 1 0 cvbs in3 c in 1 0 1 1 cvbs in4 c in 1 1 0 0 cvbs in5 c in 1 1 0 1 y in 1 c in 1 1 1 0 y in 2 c in 2 1 1 1 y in 3 c in 3
NJW1340 -5- ? ? ? ? equivalent circuit no. symbol function inside equivalent circuit voltage 1 3 5 cin1 cin2 cin3 chroma signal input 200 20k 2.8v 7 9 11 13 15 17 19 21 yin1 yin2 yin3 cvbsin1 cvbsin2 cvbsin3 cvbsin4 cvbsin5 y signal input, yin1 correspond to the synchronous detection at the power saving mode. composite video signal input, cvbsin1 correspond to the synchronous detection at the power saving mode. 200 2.5v 4 power save power save control 1 6k 34k 16 detsw signal detection control, y in1 or cvbs in1 8k 40k
NJW1340 - 6 - no. symbol function inside equivalent circuit voltage 22 mminteg capacitor connection for smoothing mono multi. 200 1 0k 23 mmtc capacitor and resistance connection for mono multi time constant. the accuracy of external resistance recommends within 5%. 200 32k 24 clamp capacitor connection for clamp 225 0.9v 25 clamp capacitor connection for clamp 48k 200 1.3v
NJW1340 -7- no. symbol function inside equivalent circuit voltage 26 scl i 2 c clock 4k 27 sda i 2 c data 4k 28 address slave address setting 66 29 31 out1 out2 composite video signal, y signal output chroma signal output 56 0.9v 2.0v
NJW1340 - 8 - no. symbol function inside equivalent circuit voltage 29 detout detection signal output. the synchronous detection result output at the power saving mode. 1 00k 6 8 10 12 14 18 30 gnd gnd 20 vcc1 vcc2 vcc
NJW1340 -9- ? ? ? ? test circuit (note) it the following refers when the synchronous signal detection unused. 16pin detsw open 22pin mminteg open 23pin mmtc open 24pin clamp open 25pin clamp open 32pin detout open 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 + 75 ? 0.1uf + 75 ? 0.1uf + 75 ? 0.1uf + + 0.1uf + 75 ? + 75 ? + 75 ? 1uf + 75 ? + 1uf + 75 ? + 1uf + 75 ? + 1uf + 75 ? + 1uf 10k ? + 10uf 32 32 32 10k ? + 10uf 75 ? + 1uf 75 ? + 1uf 75 ? + 1uf + + 3.3uf 1uf cin1 cin2 cin3 yin1 yin2 yin3 cvbsin1 cvbsin2 detsw vc c1 power save gnd cvbsin3 cvbsin4 cvbsin5 detout clamp mminteg mmtc 1nf gnd vcc2 scl sda address out1 gnd out2 50k ?
NJW1340 - 10 - typical characteristics [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -50 -40 -30 -20 -10 0 10 5 10 6 10 7 voltage gain vs frequency gain [db] freq [mhz]
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